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3rd party header and footer Solutions Products Support Solutions Products Support Solutions Products Support Solutions Products Support Solutions Products Support Account My Account Create Account Sign Out Search All Silicon Devices Boards and Kits Intellectual Property Support Documentation Knowledge Base Community Forums Partners Videos Press Search Browse Sign In Help Community Forums All community Users cancel Turn on suggestions Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. Showing results for Show only | Search instead for Did you mean: 835 Members Online 179K Discussions 53.6K Solutions Welcome to the Xilinx Community Forums! Please log in to learn, participate, and share in the community. Not a member? Join Now! Before you post please read our Community Forums Guidelines or to get started see our Community Forum Help. Community Activity Latest activity Solved Kudoed Post a Question How to simulate with C language on SDK in the non-project by luoxi213 Visitor in High-Level Synthesis (HLS) 03-08-2021 0 0 0 0 function abnormal at board level, crack is found after remove the device by Tiffanyluo Newbie in FPGA Configuration 03-08-2021 0 0 0 0 Testing 100G MRMAC on VCK190 ES1 with spirent C50 instrument by RuashTime Observer in Ethernet 03-08-2021 0 2 0 2 对于zcu102开发板 ，如果要外接usb camera，jumper怎么连接？ by bestcarp Visitor in Xilinx评估板 03-08-2021 0 1 0 1 输入时钟与IBUFDS问题 by yangxc Visitor in Vivado 03-08-2021 0 10 0 10 Essential bits generation with Vitis Flow by dag Observer in Vitis Acceleration, SDAccel, SDSoC 03-08-2021 0 1 0 1 Issues with petalinux-utils --gdb by rwk Visitor in Embedded Linux 03-08-2021 0 3 0 3 ibert IP测试a750T的高速收发器发现近端PCS误码率高而近端PMA误码率低的问题 by wangli1 Visitor in 其他IP应用 03-08-2021 0 8 0 8 Ubuntu18.04安装vivado2020.1报错 by iwbhatt@mail.ustc.edu.cn Visitor in Vivado 03-08-2021 0 2 0 2 Best hardware for a relatively big Vivado project by mmatusov Voyager in Implementation 03-08-2021 0 9 0 9 Found total 0 card(s), 0 are usable by magiclamp Visitor in Alveo™ Accelerator Cards 03-08-2021 0 1 0 1 为什么代码中信号名声明前面加mark_debug=true信号还是被优化了，抓信号的时候找不到该信号？ by zhoujw Newbie in Vivado 03-08-2021 0 4 0 4 XCKU060 by Phionx Visitor in 其他FPGA器件架构 03-08-2021 0 0 0 0 Xapp524里面的参数C_FrmPattern设置问题 by hongh Moderator in Vivado 03-08-2021 0 0 0 0 Xapp524里面的参数C_FrmPattern设置问题 by qiwenbo Visitor in 其他FPGA器件架构 03-08-2021 0 0 0 0 Embedded RDMA Enabled NIC License Issue by Alex-7x Newbie in Installation and Licensing 03-08-2021 0 0 0 0 复位引脚布线失败 by lee1 Visitor in Vivado 03-08-2021 0 4 0 4 Usage of AXI-Interrupt controller - DPU-TRD Vitis-AI flow by deepg799 Explorer in AI and Vitis AI 03-08-2021 0 7 0 7 Solarflare X2541 (100G) fails to connect to 4 x 25 Gbps on 2522-25G-PLUS by amy_HS Visitor in Ethernet 03-08-2021 0 2 0 2 clocking Wizard IP核VCO问题 by tom Observer in Vivado 03-08-2021 0 2 0 2 FPGA加载不成功 by youyouyu Visitor in 其他FPGA器件架构 03-08-2021 0 2 0 2 Ubuntu has installed SDX of 2018.2, but it does not launch by eric11 Newbie in Design Entry 03-08-2021 0 3 0 3 光纤传输问题 by zm19911223 Explorer in 嵌入式 硬件系统开发 03-08-2021 0 1 0 1 Vivado xdc file by rlingemann Visitor in Xilinx Evaluation Boards 03-08-2021 0 5 0 5 "Register / Latch pins need pulse width check" on GTP in Vivado by fbdxilinxfbn Visitor in Timing Analysis 03-08-2021 0 6 0 6 Constraints Wizard: Output Constraints by joe306 Scholar in Timing Analysis 03-08-2021 0 1 0 1 Yolov3 Darknet Caffe XY coord issue on non square cfg by lucc2 Participant in AI and Vitis AI 03-08-2021 0 1 0 1 ps7_init command takes a long time in remote access by fmoraes Visitor in Embedded Development Tools 03-08-2021 0 1 0 1 pulse_width_clock check_timing warning for GigE IP in Artix 7 by 11223344 Observer in Timing Analysis 03-08-2021 0 5 0 5 xbmgmt flash U250 by pasmith50 Visitor in Alveo™ Accelerator Cards 03-08-2021 0 8 0 8 Load more New solutions Subject Author clocking Wizard IP核VCO问题 Vivado tom VCU118 DDR4 use issue Memory Interfaces and NoC crystal9182 Ultrascale FPGAs Transceivers Wizard 1.7 - selecti... Serial Transceivers sallwine pulse_width_clock check_timing warning for GigE IP... Timing Analysis 11223344 Vitis 2020.2 install with Ubuntu 20.04LTS, hangs o... Installation and Licensing lean_forward Find More Solutions Community Browser Community Forums Blogs 日本語ブログ Design and Debug Techniques Blog AI and Machine Learning Blog Data Center Blog Xilinx Xclusive Blog Adaptable Advantage Blog Forums Hardware Development Software Development and Acceleration Embedded Software Development Vivado RTL Development About Our Community 赛灵思中文社区论坛 博客 学习与培训 硬件开发 RTL 开发 综合讨论与翻译 嵌入式系统 软件开发与加速 Top Kudoed Authors Member Kudos drjohnsmith 83 avrumw 59 watari 57 View All &gg Top Kudoed Posts Subject Kudos Opening a World of Possibilities: Vitis HLS Front-... HOT!!! Re: Reset FPGA user data but keep the program with... 5 Re: Creating a Generated Clock SDC 5 ビデオ ブログ - ZCU106 ボードに UHD-SDI TX サブシステムを含む TX のみのデ... 5 Re: Why "Xilinx" choose to organize FPGAs into mul... 5 View All &gg Top Solution Authors Member Solutions miker 32 drjohnsmith 19 bruce_karaffa 16 avrumw 15 karnanl 14 View All &gg Quick links Register Sign In Users Online Currently online: 99 members 738 guests Recent signins: maps-mpls cuijunlang05183 7 terryn LuckyLuo RuashTime Please welcome our newest community members: Tiffanyluo ITANGTANGI TPridy jsandoval62 rlfranke View All &gg English 日本語 简体中文 Connect on LinkedIn Follow us on Twitter Connect on Facebook Watch us on YouTube Subscribe to Newsletter English 日本語 简体中文 © 2021 Xilinx Privacy Legal Supply Chain Transparency Contact...
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